The present application includes the entire content of Japanese Patent Application No. 2000-281725 filed on Sep. 18, 2000.
The present invention relates to a ferroelectric memory device, a method of manufacturing the same, and an embedded device. More particularly, the present invention relates to a simple matrix ferroelectric memory device using only ferroelectric capacitors instead of cell transistors, a method of manufacturing the same, and an embedded device.
A simple matrix memory cell array using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory cell array has been expected.
An objective of the present invention is to provide a ferroelectric memory device including a desired memory cell array, a method of manufacturing the same, and an embedded device.
A ferroelectric memory device according to the present invention comprises:
a memory cell array in which memory cells are arranged in a matrix, the memory cell array including first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes; and
a peripheral circuit section for selectively writing information into or reading information from the memory cell,
wherein the memory cell array and the peripheral circuit section are disposed in different layers, and
wherein the peripheral circuit section is formed in a region outside the memory cell array.
In the present invention, the peripheral circuit section is formed in a region outside the memory cell array. Therefore, a semiconductor substrate below the memory cell array is planar. As a result, a planar interlayer dielectric can be easily formed on the semiconductor substrate. Therefore, the memory cell array can be formed reliably on the planar interlayer dielectric, whereby a memory cell array with a desired pattern can be easily formed.
In the present invention, the ferroelectric layer may have any of the following three features.
(1) The ferroelectric layer may be disposed linearly along the first signal electrodes. Specifically, the ferroelectric layer may be selectively disposed over the first signal electrodes. In this case, since the ferroelectric layer is formed linearly along the first signal electrodes, the parasitic capacitance or load capacitance of the second signal electrodes can be decreased.
The memory cells may be disposed over a base, and a dielectric layer may be provided between laminates formed of the first signal electrodes and the ferroelectric layer so as to cover exposed areas of the base.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
A surface-modifying layer having a surface characteristic differing from a surface characteristic of a surface of the base may be formed over the base.
The surface-modifying layer may be disposed in regions in which the memory cells are not formed and may have a surface exhibiting weaker affinity to a material which forms the memory cells than a surface of the base. The surface-modifying layer may be disposed in regions in which the memory cells are formed and may have a surface exhibiting stronger affinity to a material which forms the memory cells than a surface of the base.
(2) The ferroelectric layer may be disposed linearly along the second signal electrodes. Specifically, the ferroelectric layer may be selectively disposed under the second signal electrodes. In this case, since the ferroelectric layer is formed linearly along the second signal electrodes, the parasitic capacitance or load capacitance of the first signal electrodes can be decreased.
The memory cells may be disposed over a base, and a dielectric layer is provided between laminates formed of the ferroelectric layer and the second signal electrode so as to cover exposed areas of the base and the first signal electrodes.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
(3) The ferroelectric layer may be disposed only in the intersection regions between the first signal electrodes and the second signal electrodes. In this case, since the ferroelectric layer is formed in the smallest region, the parasitic capacitance or load capacitance of the signal electrodes can be further decreased.
The memory cells may be disposed over a base, and a dielectric layer may be provided between laminates formed of the first signal electrodes and the ferroelectric layer so as to cover part of exposed areas of the base.
The exposed areas of the base and the first signal electrodes may be covered with the dielectric layer over the base.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
A surface-modifying layer having a surface characteristic differing from a surface characteristic of a surface of the base may be formed over the base.
The surface-modifying layer may be disposed in regions in which the memory cells are not formed and may have a surface exhibiting weaker affinity to a material which forms the memory cells than a surface of the base. The surface-modifying layer may be disposed in regions in which the memory cells are formed and may have a surface exhibiting stronger affinity to a material which forms the memory cells than a surface of the base.
The ferroelectric memory device of the present invention may have the following configurations.
(A) The ferroelectric memory device may comprise an insulating base,
the memory cell array may comprise the first signal electrodes provided in grooves formed in the insulating base, the ferroelectric layer, and the second signal electrodes, and
the ferroelectric layer and the second signal electrodes may be layered over the insulating base in which the first signal electrodes are formed.
The insulating base used herein refers to a base of which at least the surface area on which the first signal electrodes are formed has insulating properties. The insulating base may be a base formed of a conductive material of which only the surface area is provided with insulating properties (hereinafter the same).
(B) The memory cell array may comprise an insulating base, and
depressed sections and projected sections may be provided to the insulating base in a given pattern,
the first signal electrodes may be disposed at a bottom of the depressed sections and on the upper surface of the projected sections, and
the ferroelectric layer and the second signal electrodes may be stacked over the insulating base over which the first signal electrodes are formed.
(C) A plurality of unit blocks of the above ferroelectric memory device may be arranged in a given pattern.
(D) The ferroelectric memory device may comprise a plurality of memory cell arrays, and
the plurality of memory cell arrays may be layered.
(E) Insulation layers may be provided between the first signal electrodes, and the upper surfaces of the first signal electrodes may be on the same level as upper surfaces of the insulation layers.
Manufacturing Method of Ferroelectric Memory Device
A method of manufacturing a ferroelectric memory device comprises steps of:
(a) forming a peripheral circuit section for selectively writing information into or reading information from the memory cell over a semiconductor substrate; and
(b) forming at least first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and forming a memory cell array in which memory cells are arranged in a matrix,
wherein the peripheral circuit section is formed in a region outside the memory cell array.
The step (b) may comprise steps of: (b-1) forming the first signal electrodes; (b-2) forming the ferroelectric layer; and (b-3) forming the second signal electrodes.
The step (b-2) may comprise a step of forming an amorphous ferroelectric layer or a microcrystalline ferroelectric layer, and a step of forming the ferroelectric layer by subjecting the amorphous ferroelectric layer or the microcrystalline ferroelectric layer to a heat treatment. In the case of forming the ferroelectric layer by using selective growth, this enables the ferroelectric layer to be selectively grown at a lower temperature in comparison with other formation methods.
The step (b-2) may have any of the following features.
(1) As the first feature, the step (b-2) may be a step of forming the ferroelectric layer linearly along the first signal electrodes.
In this feature, the method may comprise:
a step of forming, over a base, a first region having a surface characteristic which causes a material for forming at least one of the first signal electrodes or the ferroelectric layer to be deposited preferentially, and a second region having a surface characteristic which causes a material for forming at least one of the first signal electrodes or the ferroelectric layer to be less deposited than the first region; and
a step of providing a material for forming at least one of the first signal electrodes or the ferroelectric layer and selectively forming the material in the first region.
The first region and the second region may be formed on a surface of the base.
A surface of the base may be exposed in the first region, and
a surface-modifying layer that has a surface characteristic exhibiting weaker affinity to the material for forming the first signal electrodes and the ferroelectric layer than the exposed surface of the base in the first region may be formed in the second region.
A surface of the base may be exposed in the second region, and
a surface-modifying layer that has a surface characteristic exhibiting stronger affinity to the material for forming the first signal electrodes and the ferroelectric layer than the exposed surface of the base in the second region may be formed in the first region.
A dielectric layer may be provided between laminates formed of the first signal electrodes and the ferroelectric layer so as to cover exposed areas of the base.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
(2) As a second feature, the ferroelectric layer and the second signal electrodes may be formed in a direction intersecting the first signal electrodes, and
the ferroelectric layer may be formed linearly along the second signal electrodes.
In this feature, the ferroelectric layer and the second signal electrodes may be patterned by etching using the same mask.
A dielectric layer may be provided between laminates formed of the ferroelectric layer and the second signal electrode so as to cover exposed areas of the base and the first signal electrodes.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
(3) As a third feature, The method may comprise a step (b-4) of patterning the ferroelectric layer after the step (b-3), and causing the ferroelectric layer to remain in a shape of a block only in intersecting regions between the first signal electrodes and the second signal electrodes.
In this case, the method may comprise:
a step of forming, over the base, a first region having a surface characteristic which causes a material for forming at least one of the first signal electrodes or the ferroelectric layer to be deposited preferentially, and a second region having a surface characteristic which causes a material for forming at least one of the first signal electrodes or the ferroelectric layer to be less deposited than the first region; and
a step of providing a material for forming at least one of the first signal electrodes or the ferroelectric layer and selectively forming the material in the first region.
The first region and the second region may be formed on a surface of the base.
A surface of the base may be exposed in the first region, and
a surface-modifying layer that has a surface characteristic exhibiting weaker affinity to the material for forming the first signal electrodes and the ferroelectric layer than the exposed surface of the base in the first region may be formed in the second region.
A surface of the base may be exposed in the second region, and
a surface-modifying layer that has a surface characteristic exhibiting stronger affinity to the material for forming the first signal electrodes and the ferroelectric layer than the exposed surface of the base in the second region may be formed in the first region.
The ferroelectric layer and the second signal electrodes may be patterned by etching using the same mask.
A dielectric layer may be provided between laminates formed of the first signal electrodes and the ferroelectric layer so as to cover exposed areas of the base.
A dielectric layer may be provided between laminates formed of the ferroelectric layer and the second signal electrode so as to cover exposed areas of the base and the first signal electrodes.
The dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer.
The method of manufacturing a ferroelectric memory device of the present invention may further comprise the following step.
The method may comprise a step (b-5) of forming insulation layers between the first signal electrodes after the step (b-1), and
upper surfaces of the insulation layers may be on the same level as upper surfaces of the first signal electrodes.
Inclusion of the step (b-5) enables the ferroelectric layer to be formed on the planar surface. Therefore, a ferroelectric layer with a desired pattern can be easily formed.
Specifically, the step (b-5) may be a step of forming the insulation layers using a solution application process and planarizing the insulation layers.
Embedded Device
An embedded device of the present invention comprises:
the ferroelectric memory device of the present invention, and
at least one component selected from a group including a flash memory, a processor, an analog circuit, and an SRAM.